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? xicor, inc. 2000 patents pending 9900-5004.9 5/26/00 ep characteristics subject to change without notice. 1 of 15 16k X25170 2k x 8 bit spi serial e 2 prom with block lock ? protection features ?5mhz clock rate ?spi modes (0,0 & 1,1) ?2k x 8 bits ? 32 byte page mode ?low power cmos ? <1a standby current ?<5ma active current ?2.5v to 5.5v power supply ?block lock protection ?protect 1/4, 1/2 or all of e 2 prom array ? built-in inadvertent write protection ? power - up/power - down protection circuitry ?write enable latch ? write protect pin ?self-timed write cycle ? 5ms write cycle time (typical) ?high reliability ? endurance: 100,000 cycles ?data retention: 100 years ? esd protection: 2000v on all pins ?8-lead pdlp package ?8-lead soic package ? 14-lead tssop package description the X25170 is a cmos 16384-bit serial e2prom , internally organized as 2k x 8. the X25170 features a serial peripheral interface (spi) and software prot ocol, allowing operation on a simple three-wire bus. the bus signals ar e a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs) input, allowing any number of devices to share the same bus. the X25170 also features two additional inputs that provide the end user with added flexibility. by ass erting the hold input, the X25170 will ignore transitions on its inputs, thus allowing the host to service higher pr ior- ity interrupts. the wp input can be used as a hardw ire input to the X25170 (disabling all write attempts to the status register), thus providing a mechanism for li miting end user capability of altering 0, 1/4, 1/2 or all of t he memory. the X25170 utilizes xicor?s proprietary direct write cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. ? direct write ? and block lock ? protection is a trademark of xicor, inc. block diagram command decode and control logic write control and timing logic write protect logic x decode logic 2k byte array 16 x 256 y decode data register so si sck cs hold wp 16 32 8 32 status register 16 32 x 256 16 x 256 ic mic ic microsystems tm this X25170 device has been acquired by ic microsystems from xicor, inc. www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 2 of 15 pin descriptions serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte addresses, and data to be written to the memory are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the serial clock controls the serial bus timing for data input and output. opcodes, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin change after the falling edge of the clock input. chip select (cs ) it should be noted that after power-up, a high to low transition on cs is required prior to the start of any operation. when cs is high, the X25170 is deselected and the so output pin is at high impedance; unless an internal write operation is underway, the X25170 will be in the standby power mode. cs low enables the X25170, placing it in the active power mode. write protect (wp ) when wp is low and the nonvolatile bit wpen is ?? nonvolatile writes to the X25170 status register are dis- abled, but the part otherwise functions normally. when wp is held high, all functions, including nonvolatile writes operate normally. wp going low while cs is still low will interrupt a write to the X25170 status reg- ister. if the internal write cycle has already been initi- ated, wp going low will have no effect on a write. the wp pin function is blocked when the wpen bit in the status register is ?? this allows the user to install the X25170 in a system with wp pin grounded and still be able to write to the status register. the wp pin func- tions will be enabled when the wpen bit is set ?? pin names pin configuration hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume com- munication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. symbol description cs chip select input so serial output si serial input sck serial clock input wp write protect input v ss ground v cc supply voltage hold hold input nc no connect tssop nc 1 2 3 4 7 6 5 X25170 v ss nc nc nc nc 8 9 10 11 12 14 13 nc dip/soic v cc hold sck cs 1 2 3 4 6 7 8 X25170 v ss si 5 so wp cs so wp v cc hold sck si www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 3 of 15 principles of operation the X25170 is a 2k x 8 e 2 prom designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. the X25170 contains an 8-bit instruction register. it is accessed via the si input, with data being clocked in on the rising sck. cs must be low and the hold and wp inputs must be high during the entire opera- tion. the wp input is ?on? care if wpen is set ?? table 1 contains a list of the instructions and their opcodes. all instructions, addresses and data are transferred msb ?st. data input is sampled on the ?st rising edge of sck after cs goes low. sck is static, allowing the user to stop the clock and then resume operations. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input to place the X25170 into a ?ause condition. after releasing hold , the X25170 will resume operation from the point when hold was ?st asserted. write enable latch the X25170 contains a ?rite enable latch. this latch must be set before a write operation will be com- pleted internally. the wren instruction will set the latch and the wrdi instruction will reset the latch. this latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status reg- ister write cycle. status register the rdsr instruction provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is format- ted as follows: wpen, bp0 and bp1 are set by the wrsr instruction. wel and wip are read-only and automatically set by other operations. the write-in-process (wip) bit indicates whether the X25170 is busy with a write operation. when set to a ?? a write is in progress, when set to a ?? no write is in progress. during a write, all other bits are set to ?? the write enable latch (wel) bit indicates the status of the ?rite enable latch. when set to a ?? the latch is set, when set to a ?? the latch is reset. the block protect (bp0 and bp1) bits are nonvolatile and allow the user to select one of four levels of protec- tion. the X25170 is divided into four 4096-bit seg- ments. one, two, or all four of the segments may be protected. that is, the user may read the segments but will be unable to alter (write) data within the selected segments. the partitioning is controlled as illustrated in the following table. 76543210 wpen x x x bl1 bl0 wel wip status register bits array addresses protected bp1 bp0 0 0 none 0 1 $0600?07ff 1 0 $0400?07ff 1 1 $0000?07ff table 1. instruction set notes: *instructions are shown msb in leftmost position. instructions are transferred msb ?st. instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operations) wrdi 0000 0100 reset the write enable latch (disable write operations) rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address (1 to 32 bytes) www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 4 of 15 write-protect enable the write-protect-enable (wpen) bit is available for the X25170 as a nonvolatile enable bit for the wp pin. the write protect (wp ) pin and the nonvolatile write protect enable (wpen) bit in the status register con- trol the programmable hardware write protect feature. hardware write protection is enabled when wp pin is low, and the wpen bit is ?? hardware write protec- tion is disabled when either the wp pin is high or the wpen bit is ?? when the chip is hardware write pro- tected, nonvolatile writes are disabled to the status register, including the block protect bits and the wpen bit itself, as well as the block-protected sections in the memory array. only the sections of the memory array that are not block-protected can be written. note: since the wpen bit is write protected, it cannot be changed back to a ?? as long as the wp pin is held low. wpen wp wel protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable clock and data timing data input on the si line is latched on the rising edge of sck. data is output on the so line by the falling edge of sck. read sequence when reading from the e 2 prom memory array, cs is ?st pulled low to select the device. the 8-bit read instruction is transmitted to the X25170, followed by the 16-bit address of which the last 11 are used. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached ($07ff), the address counter rolls over to address $0000, allowing the read cycle to be continued inde?itely. the read operation is terminated by taking cs high. refer to the read e2prom array operation sequence illustrated in figure 1. to read the status register the cs line is ?st pulled low to select the device followed by the 8-bit rdsr instruction. after the rdsr opcode is sent, the con- tents of the status register are shifted out on the so line. the read status register sequence is illustrated in figure 2. www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 5 of 15 figure 1. read e 2 prom array operation sequence figure 2. read status register operation sequence 012 3456 78910 2021222324252627282930 7 65432 10 data out cs sck si so msb high impedance instruction 16 bit address 15 14 13 3 2 1 0 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction write sequence prior to any attempt to write data into the X25170, the ?rite enable latch must ?st be set by issuing the wren instruction (see figure 3). cs is ?st taken low, then the wren instruction is clocked into the X25170. after all eight bits of the instruction are trans- mitted, cs must then be taken high. if the user con- tinues the write operation without taking cs high after issuing the wren instruction, the write operation will be ignored. to write data to the e 2 prom memory array, the user issues the write instruction, followed by the address and then the data to be written. this is minimally a thirty-two clock operation. cs must go low and remain low for the duration of the operation. the host may continue to write up to 32 bytes of data to the X25170. the only restriction is the 32 bytes must reside on the same page. if the address counter reaches the end of the page and the clock continues, the counter will ?oll over to the ?st address of the page and overwrite any data that may have been written. www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 6 of 15 figure 3. write enable latch sequence 01234567 cs si sck high impedance so for the write operation (byte or page write) to be com- pleted, cs can only be brought high after bit 0 of data byte n is clocked in. if it is brought high at any other time the write operation will not be completed. refer to figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which cs going high are valid. figure 4. byte write operation sequence 012345678910 cs sck si so high impedance instruction 16 bit address data byte 76543210 151413 3210 20 21 22 23 24 25 26 27 28 29 30 31 to write to the status register, the wrsr instruction is followed by the data to be written. data bits 0, 1, 4, 5 and 6 must be ?? this sequence is shown in figure 6. while the write is in progress following a status register or e 2 prom write sequence, the status register may be read to check the wip bit. during this time the wip bit will be high. hold operation the hold input should be high (at v ih ) under normal operation. if a data transfer is to be interrupted hold can be pulled low to suspend the transfer until it can be resumed. the only restriction is the sck input must be low when hold is ?st pulled low, and sck must also be low when hold is released. the hold input may be tied high either directly to v cc or tied to v cc through a resistor. www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 7 of 15 figure 5. page write operation sequence figure 6. write status register operation sequence 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 data byte n 15 14 13 3210 20 21 22 23 24 25 26 27 28 29 30 31 6543210 0123456789 cs sck si so high impedance instruction data byte 765432 10 10 11 12 13 14 15 operational notes the X25170 powers-up in the following state: the device is in the low power standby state. a high to low transition on cs is required to enter an active state and receive an instruction. so pin is high impedance. the ?rite enable latch is reset. data protection the following circuitry has been included to prevent inadvertent writes: the ?rite enable latch is reset upon power-up. a wren instruction must be issued to set the ?rite enable latch. ?s must come high at the proper clock count in order to start a write cycle. www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 8 of 15 absolute maximum ratings temperature under bias ........................?5 to +135 c storage temperature .............................?5 to +150 c voltage on any pin with respect to v ss ....... ?v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds).........300 c comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0? +70? industrial ?0? +85? military ?5? +125? supply voltage limits X25170 5v 10% X25170-2.5 2.5v to 5.5v d.c. operating characteristics (over the recommended operating conditions unless otherwise speci?d.) power-up timing symbol parameter limits units test conditions min. max. i cc v cc supply current (active) 5 ma sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open, cs = v ss so = open, cs = v ss so = open, cs = v ss i sb v cc supply current (standby) 1 acs = v cc , v in = v ss or v cc i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v il (1) input low voltage ? v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v v cc = 5v, i ol = 3ma v oh1 output high voltage v cc ?.8 v v cc = 5v, i oh = -1.6ma v ol2 output low voltage 0.4 v v cc = 2.70v, i ol = 1.5ma v oh2 output high voltage v cc ?.3 v v cc = 2.70v, i oh = -0.4ma symbol parameter min. max. units t pur (3) power-up to read operation 1 ms t puw (3) power-up to write operation 1 ms www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 9 of 15 capacitance t a = +25 c, f = 1mhz, v cc = 5v notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. (3) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter max. units test conditions c out (2) output capacitance (so) 8 pf v out = 0v c in (2) input capacitance (sck, si, cs , wp , hold ) 6 pf v in = 0v equivalent a.c. load circuit a.c. conditions of test output 5v 1.44k ? 1.95k ? 100pf output 3v 1.64k ? 4.63k ? 100pf input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 a.c. characteristics (over recommended operationg conditions, unless otherwise speci?d.) data input timing symbol parameter min. max. units f sck clock frequency 0 5 mhz t cyc cycle time 200 ns t lead cs lead time 100 ns t lag cs lag time 100 ns t wh clock high time 80 ns t wl clock low time 80 ns t su data setup time 20 ns t h data hold time 20 ns t ri (4) data in rise time 2 s t fi (4) data in fall time 2 s t hd hold setup time 40 ns t cd hold hold time 40 ns t cs cs deselect time 100 ns t wc (5) write cycle time 10 ms www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 10 of 15 data output timing notes: (4) this parameter is periodically sampled and not 100% tested. (5) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle serial output timing serial input timing symbol parameter min. max. units f sck clock frequency 0 5 mhz t dis output disable time 100 ns t v output valid from clock low 80 ns t ho output hold time 0 ns t ro (4) output rise time 50 ns t fo (4) output fall time 50 ns t lz (4) hold high to output in low z 50 ns t hz (4) hold low to output in high z 50 ns sck cs so si msb out msb? out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 11 of 15 hold timing symbol table sck cs si so t hd t lz hold t hz t cd t hd t cd must be steady will be steady may change from low will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance waveform inputs outputs www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 12 of 15 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional .073 (1.84) max. 0.325 (8.25) 0.300 (7.62) plane www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 13 of 15 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0?- 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 14 of 15 packaging information note: all dimensions in inches (in p arentheses in millimeters) 14-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0?- 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) www.datasheet.co.kr datasheet pdf - http://www..net/
X25170 characteristics subject to change without notice. 15 of 15 limited warranty devices sold by xicor, inc. are covered by the warranty and pa tent indemnification provisions appearing in its terms o f sale only. xicor, inc. makes no warranty, express, statuto ry, implied, or by description regarding the information set forth herein or regarding the freedom of the desc ribed devices from patent infringement. xicor, inc. make s no warranty of merchantability or fitness for any purpose. xicor, inc. re serves the right to discontinue production and change spec ifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any cir cuitry other than circuitry embodied in a xicor, inc. p roduct. no other circuits, patents, or licenses are implie d. trademark disclaimer: xicor and the xicor logo are registered trademarks of xi cor, inc. autostore, direct write, block lock, serialflash , mps, and xdcp are also trademarks of xicor, inc. all o thers belong to their respective owners. u.s. patents xicor products are covered by one or more of the foll owing u.s. patents: 4,326,134; 4,393,481; 4,404 ,475; 4,450,402; 4,486,769; 4,488,060; 4,520,46 1; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,9 67; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,0 23,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,4 09; 5,977,585. foreign patents and additional patent s pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence . xicor?s products are not authorized for use in critical co mponents in life support devices or systems. 1. life support devices or systems are devices or systems which, (a ) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perfo rm, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life suppor t device or system whose failure to perform can be reason ably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ordering information part mark convention X25170 p g - v device v cc limits blank = 5v 10% 2.5 = 2.5v to 5.5v temperat ure range blank = commercial = 0 c to +70 c package s8 = 8-lead soic t i = industrial = ?40 c to +85 c x g g = rohs compliant lead free x blank = 5v 10%, 0c to +70c ae = 2.5v to 5.5v, 0c to +70c i = 5v 10%, ?40c to +85c af = 2.5v to 5.5v, ?40c to +85c X25170 g = r ohs compl ian t lead - free package blank = standard package. non lead-free blank = 8-lead soic www.datasheet.co.kr datasheet pdf - http://www..net/

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